Module 5 · Memory management · Project 45
Every addresstakes a route.Watch it travel.
A memory-management unit you can probe one byte at a time. Split addresses into bits, watch the TLB answer or miss, follow the page walk, catch faults, then rewind time and replay the same run under a different machine.
- 6
- replacement policies
- 4
- page-table levels
- 96
- automated tests
- 32
- bit address space
The journey
Nine connected rooms
Each page does one job. Your machine, timeline and results travel with you from page to page, so a change in one room shows up in every other.
Machine
Configure the hardware: address widths, page size, TLB size, associativity, policy, page faults, processes and timing.
02Translate
Probe one address. Get the answer instantly, or watch the full calculation play step by step.
03Timeline
Run whole workloads, scrub through time like a logic analyzer, and branch “what if” runs.
04Structures
Look inside the TLB sets and ways, the page-table map and physical memory frames.
05Analytics
Hit ratio over time, outcome mix and effective access time, modelled vs measured.
06Policy lab
Run one trace through six policies and seven sizes. Belady’s anomaly is flagged automatically.
07Learn
Field notes, viva drill, real-world applications and the mapping to real CPUs.
08Self-test
96 automated checks of the engine, run live in your browser.
09Report
A clean, print-ready A4 report of your session. Save it as a PDF.